1. Field of the Invention
The present invention relates to a method and apparatus for testing integrated circuits (ICs).
2. Description of the Background Art
Integrated circuits are produced by the millions. A zero error rate is required for some applications, for example, in integrated circuits for safety-relevant functions such as the control of an airbag release. For this reason, each individual integrated circuit, which is intended for this type of application, is tested for its proper function after being manufactured. In a few safety-critical applications as well, production must be tested at least by spot checking, which in the case of the indicated quantities still produces very high numbers of integrated circuits to be tested.
In conventional testing methods, there is a requirement that after a change in the input signal a fixed waiting time must pass before a measured value of an output signal reaction is detected that is then used as a predetermined condition. This waiting time takes into account a production series-specific delay, with which integrated circuits respond to a stimulating input signal change. Actual delays, which occur in individual circuits, can have deviations due to deviations of the component parameters in different representatives of a series of integrated circuits from the same production series, so that some integrated circuits respond earlier and other integrated circuits respond later to an input signal change.
To enable a reliable differentiation between good and bad integrated circuits, the fixed waiting time must be predetermined so that, also within the scope of permitted fluctuations, integrated circuits that respond admittedly more slowly but always with still sufficient speed can still be recognized as being good. The result is that measured values for rapidly responding components within the scope of permitted fluctuations are received unnecessarily late, which in fact is not critical for the quality of the measurement, but lengthens the measuring time required for testing a large number of similar integrated circuits. This lengthening of the test time reduces the throughput of an individual testing apparatus, so that more testing apparatuses must be provided for a preset rate for testing integrated circuits. The lengthened measuring time must therefore be absorbed in higher investment for more testing apparatuses, associated manipulating systems, mounting surfaces, power supply, etc.